1. Field of the Invention
The present invention concerns an operational amplifier equipped with an offset cancel function. Further, it also relates to a line driver for a liquid crystal display device equipped with an offset cancel function and a liquid crystal display device
2. Description of Related Art
In an operational amplifier, an offset voltage is sometimes generated by scattering of current-voltage characteristics of constitutional transistors. Generation of the offset voltage is not preferred in view of characteristics of the operational amplifier. For example, in a source drive circuit of a liquid crystal display device in which plural operational amplifiers drive plural data lines, the output voltage of the operational amplifier is sometimes different even for an identical input voltage, which causes color shading of displayed images. Accordingly, it is necessary to suppress offset of the operational amplifier.
JP-A No. 2003-168936 discloses an operational amplifier circuit 100 equipped with an offset cancel function as shown in FIG. 10 and a time chart showing the operation of the operational amplifier circuit 100 shown in FIG. 11. In an offset cancel preparatory period from time t1 to time t2 in FIG. 11, switches SW101 and SW103 are turned on, while a switch SW102 is turned off. Since an output voltage VOJ is not fed back to the gate of NMOS transistors M101, and the gate voltage for NMOS transistor M101 and M102 is at an input voltage VIJ, a differential pair input circuit 115 operates as a current source to a current mirror circuit 114. On the other hand, since the output voltage VOJ is fed back to the gate of an NMOS transistor M108, a voltage follower circuit is constituted with the current mirror 114, a differential amplifier circuit comprising a differential pair input circuit 116 and an output buffer circuit 112, to conduct feed back control such that the output voltage VOJ approaches a reference voltage Vref. In this case, voltages V101 and V102 are not equal with each other due to scattering of gate oxide film thickness for MOS transistors to cause offset of displacing the output voltage VOJ from the input voltage VIJ. A capacitor C101 is charged or discharged by output voltage VOJ containing the offset and the voltage of the electrode on the side of the switch SW103 is equal with the output voltage VOJ. That is, the output voltage VOJ is stored into the capacitor C101 in the stable state thereof.
At time t2, when the switches SW101 and SW103 are turned off and the switch SW102 is turned on, operations of the differential pair input circuits 115 and 116 are inversed, and the voltage follower is constituted with the differential amplifier circuit 111 and the output buffer circuit 112, to conduct feed back operation such that the output voltage VOJ approaches the input voltage VIJ. In this case, the gate voltage of the NMOS transistor M108 is equal with the output voltage VOJ at time t2. Even when the operations of the differential pair input circuits 115 and 116 are inversed, since the differential pair input circuits 115 and 116 are connected in parallel with the current mirror 114 and the gate voltage of the NMOS transistors M102, M108 and M109 is equal with the voltage in the stable state just before switching at time t2, feed back control for the voltage of the NMOS transistor M101 is stabilized in a state where it is aligned with the input voltage VIJ which is a voltage just before the switching. That is, the offset voltage is canceled and an output voltage VOJ equal with the input voltage VIJ is outputted.
Further, JP-A No. 2003-168936 discloses the schematic constitution of a liquid crystal display device using an operational amplifier circuit equipped with an offset cancel function as a data driver (line driver) as shown in FIG. 12. In a liquid crystal display panel 120, plural data lines 121 extending in a vertical direction and plural scanning lines 122 extending in a horizontal direction are formed crossing over with each other and pixels are formed corresponding to cross over points respectively. Ends of the data lines 121 and scanning lines 122 are connected, respectively, to a data driver (line driver) 130 and a scanning driver 140 respectively. A control circuit 150 supplies display data signals and clock signals to the data driver (line driver) 130 and supplies scanning control signals to the scanning driver 140 based on video signals, pixel clock signals, horizontal sync signals and vertical sync signals supplied from the outside. The data driver (line driver) 130 outputs display data while converting to voltages of positive polarity and negative polarity relative to the ground voltage GND on every one horizontal scanning period (and on every one pixel). In the data driver (line driver) 130, voltage followers 131 of positive polarity equipped with offset cancel and voltage followers 132 of negative polarity equipped with offset cancel are formed at the output stage thereof, and connected to data lines 121 of the liquid crystal display panel 120 such that the outputs are put to parallel connection or cross over connection by the switching circuit 133 on every adjacent pairs of voltage followers equipped with offset cancel of positive and negative polarities. The voltage follower 131 equipped with offset cancel of positive polarity has an identical constitution with the operational amplifier circuit 100, and the voltage follower 132 equipped with offset cancel of negative polarity has a constitution of replacing the NMOS transistor and the PMOS transistor to each other in the operational amplifier circuit 100.
However, since a reference voltage Vref of a constant value as a reference voltage for canceling the offset of the operational amplifier is used, in a case where the voltage difference between the output voltage VOJ and the reference voltage Vref is large, it takes a much time for conducting feed back control to the output voltage VOJ containing the offset voltage. For this reason, it is necessary to take a long offset cancel preparatory period assuming such a situation. Accordingly, this hinders shortening for the offset cancel preparatory period to bring about a problem.
Further, in the liquid crystal display device, one horizontal period has to be shortened in a case where the number of display lines increases for making the liquid crystal display device finer. However, in the liquid crystal display device in JP-A No. 2003-168936, since the offset cancel preparatory period is present in one horizontal period, shortening for the entire one horizontal period is difficult to bring about a problem.